An electrostatic discharge (ESD) event may cause extremely high currents to flow through the semiconductor devices in a chip, causing device junctions, gate oxides, and other adjacent structures to be permanently damaged. Conventional methods and structures may be used to provide ESD protection during chip manufacture, including during various fabrication, testing, and packaging steps. However, ESD protection in high voltage applications, such as for example, in the user environment and field use, is still an issue of concern.
With the shrinking of device size through technology scaling, it becomes increasingly more challenging to achieve adequate protection against electrostatic discharge (ESD) for CMOS integrated circuits. Technology scaling has brought with it very low breakdown voltages in CMOS circuits. For example, in the 90 nm node, these breakdown voltages fall below 10V for transient stresses of short duration as it typically occurs in a Charged Device Model (CDM) discharge. At the same time, advances in IC technology have increased the circuit density which has led to a corresponding increase in the number of pads for off-chip connections, i.e., for chip input/outputs (I/Os) and for supplying power and ground to the chip.
Moreover, while gate oxide is getting thinner and more difficult to protect, the compatibility requirement to legacy devices remains unchanged. This limits the design window to an even smaller range. Compatibility with legacy devices requires that chips utilizing current technology offerings (e.g., 2.5V devices) communicate with older chips that use older technology (e.g., 5V devices).
In general, newer, lower-voltage ESD NFETs can no be used to protect older, higher voltage tolerant or fail-safe I/O designs. In such cases, stacked NFETs are required to make legacy-compatible designs while handling the higher voltage across the device to be protected. However, the practice of stacking 2.5V ESD NFETs to handle 5V operations (e.g., when interacting with legacy devices) suffers from reliability problems and insufficient ESD protection levels. Moreover, traditional silicided NFETs are not robust against ESD discharge and require significantly more chip area on resistance ballasting in order to handle the ESD current safely. As such, backward-compatibility (e.g., 5V-tolerant I/Os) and ESD-ruggedness in consumer electronics requires new solutions for designs manufactured in sub-micron technologies.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.